The present invention relates to a method of forming an insulative film by vacuum laminating a protective film of an insulative organic material (dry film resist) on a semiconductor substrate or an insulator substrate having device elements formed thereon.
A film of an insulative organic material (dry film resist) is often used for covering and protecting a surface of semiconductor device elements of a semiconductor device having the semiconductor device elements formed on a semiconductor substrate, or a surface of electronic parts of passive elements such as a coil and a capacitor and semiconductor device elements of ICs (integrated circuits) formed on an insulator substrate. There exist raised parts on a surface of a semiconductor substrate caused by semiconductor device elements formed thereon and on a surface of an insulator substrate having an inductor caused by a coil pattern with a thickness of several tens of microns formed thereon. These raised parts have a three dimensional structure. In an ordinary lamination process, air bubbles or voids are trapped in the spacing of this structure.
To avoid the inclusion of the air, a vacuum laminator as a lamination apparatus is known in which a protective film of an insulative organic material (dry film resist) is laminated on the semiconductor substrate or the insulator substrate. The vacuum laminator is provided with a chamber capable of producing a vacuum environment in the chamber by evacuation.
The vacuum laminator is also provided in the chamber with a membrane that can be heated and expands by regulating a pressure. One or more pairs of a substrate and a dry film resist (hereinafter also simply referred to as “a resist”), being able to be accommodated in the chamber, are introduced in the chamber and the chamber is evacuated, where the expanded membrane adhesively presses the resist against the substrate, covering the substrate with the resist.
The patent Document 1 describes an vacuum lamination and discloses a method of obtaining a substantially void free interface between a photosensitive dry film (a resist) and a substrate having a raised relief (Patent Document 1: Japanese Unexamined Patent Application Publication No. H2-226152).
In the above-described conventional technology, however, the resist accumulates (builds up) in the peripheral region of the substrate creating a swell (an elevation mentioned afterwards) of the resist in the peripheral region of the substrate as compared with the flat region in the inner area of the substrate. The device element located at the swelled place becomes off-specification due to the thick resist. Thus, the swelled places cause a problem that the number of defective device elements increase.
The swelled place of the resist in the peripheral region is caused by accumulation (build up) of the resist at the peripheral region of the substrate in the process of vacuum lamination of the resist, in which the heated and softened resist is pressed and extended outwardly by the pressure e.g., atmospheric pressure, towards the edge of the substrate closed by a PET film pressing the resist, as shown in FIG. 2 and described later. The outer edge of the substrate works as a fulcrum of force exerted by a pressure e.g., atmospheric pressure, on the portion of the diaphragm (not shown in FIG. 2) off the substrate 1, the diaphragm pushing the resist 5 against the substrate 1 through the PET film 15. As a result, the diaphragm/PET film is intensely pushed against the outer edge of the substrate, and is deformed by rising upwards at the position right inside the edge, causing build up of the pressed resist at this position. Therefore, the swelled place of the resist is generated at the peripheral region of the substrate. If a peripheral ring electrode is provided at the peripheral region of the substrate, this swelling of the resist grows further.
The following describes a peripheral ring electrode, which affects the swell of the resist in the peripheral area.
In the process of manufacturing a semiconductor device or electronic parts such as an inductor, a plating process is employed in many cases. In a case to form a metal film with a thickness of several tens of μm in particular, the plating process is usually employed. In the case of employing an electroplating process, it is needed to pass an electric current through the substrate (for example, silicon substrate or a ferrite substrate) to be plated. For application of an electric current, a peripheral ring electrode needs to be formed in the peripheral region of the substrate. The peripheral ring electrode is made in contact with an electrode of the plating apparatus in the plating process. A plating process also makes plating on this peripheral ring electrode.
As described previously, the resist accumulates (builds up) and swells in the end region of substrate in which the peripheral ring electrode is arranged. This means a large elevation of resist, that is, a large difference in height between the resist surface and the surface level of the connection terminals (packaged terminals/electrode pads) that are formed at the edge of a device element (an inductor or a semiconductor device element) adjacent to the peripheral ring electrode. This elevation of resist can be too large to meet the requirement of specification, thus increasing the number of defective devices. A large elevation of the resist makes it difficult to carry out soldering between the connection terminals of the device element and the wiring pattern of the printed circuit board.
FIG. 15 is a sectional view of an essential part of a substrate having a resist formed thereon. Although raised parts 3 formed with a pattern of plating have actually a complicated planar and sectional configuration on the surface of the device element 6, a sectional configuration of the raised part 3 formed on one device element is represented by a block for convenience in FIG. 15.
After forming device elements 6 having a pattern of plating of raised parts 3 and a peripheral ring electrode 2 on a substrate 1, a process of vacuum lamination is conducted. The resist 5 swells thick in the region between the peripheral ring electrode 2 and the raised part 3a adjacent to the peripheral ring electrode 2. The raised part 3 is for examples a plating pattern.
The elevation Q of the resist 5 on the raised part 3a is about 30 μm to 40 μm and larger than the elevation R of the resist 5 on the raised part 3b (about 20 μm). An elevation Q exceeding 30 μm results in poor soldering performance between the connection terminal (not shown in the figure) of the device element 6 and the printed circuit board.
A substrate 1 having many device elements 6 involves a problem that the resist is too thin on the raised parts 3 that are arranged with a large distance between raised parts 3 on adjacent device elements 6. A description is made on this problem in the following.
FIGS. 16(a) and 16(b) show a structure of a device element having a resist formed thereon, in which FIG. 16(a) is a sectional view of an essential part and FIG. 16(b) is a plan view of an essential part. FIG. 16(a) is a sectional view along the line 16(a)-16(a) in FIG. 16(b).
After forming a pattern of plating of raised parts 11 (which illustrates details of the raised part 3 in FIG. 15) on one of the many device elements 6 formed on a substrate 1, a resist 5 is formed by vacuum lamination. The raised parts 11 here are obliquely arranged in a rectangular device element 6, assuming a coil conductor of an inductor. While FIG. 15 illustrates only one raised part 3 formed on a device element 6 for convenience, FIGS. 16(a), 16(b) illustrate multiple of slanted raised parts 11 formed on a device element 6, which is more similar to an actual device element.
Comparing with the thickness of resist 5 in the center of the device element 6 (the elevation S, which is the difference between the level of the surface of the raised part and the level of the surface of the resist), the thickness of resist 5 on the raised part 11 in the end region of the device element 6 (elevation P) is thinner (elevation P<elevation S). In the worst case, the plating of the pattern of the raised parts 11 is partly uncovered with the resist.
If the resist 5 is too thin or fails to cover the plating pattern, the resist 5 cannot function as a protective film, degrading reliability of the device element. The raised parts 11 of the plated pattern can be arranged not obliquely but parallel with respect to the edge line of the rectangular device element. In that case, like the case where the plated pattern is arranged obliquely, the resist 5 in the end region of a device element 6 may be too thin or fail to cover the plating, resulting in degraded reliability.
FIG. 17 is a sectional view of an essential part along the line 17-17 in FIG. 16(b). The distance W1 between the opposing raised parts 11 of adjacent device elements 6 is equal in both cases of the section along the line 16(a)-16(a) and the section along the line 17-17. Therefore, the sectional configuration of the resist 5 on the raised parts 11 in FIG. 17 is the same as in FIG. 16(a).
It is an object of the present invention to solve the above problems and provide a method of forming an insulative film, wherein accumulation (build up) of resist at a peripheral ring electrode is suppressed to reduce elevation (swell) of resist on a raised part of a device element adjacent to the peripheral ring electrode, and decrease of a thickness of resist on a raised part is decreased at an end region of a device element.
Further objects and advantages of the invention will be apparent from the following description of the invention.